1. Field of the Invention
The present invention relates to a microcomputer, and more specifically to a microcomputer effective in handling a volume of data having continuous addresses.
2. Description of Related Art
At present, microcomputers can process given instructions at a very high speed because of improved architecture. However, in the case that the microcomputer reads data from a memory or writes data to a memory, the access speed to the memory is not so high and not comparable to the instruction processing speed of the microcomputer. This is one large cause decreasing the instruction execution speed of the microcomputer.
In general, for example, microcomputers use a read/write bus cycle consisting of three basic operation states. In a first basic operation state of each read/write bus cycle, an address latch enable signal is activated so that an address latch can latch an address on an address bus. In a period from the first basic operation state to a second basic operation state of each read/write bus cycle, the microcomputer outputs an address to the address bus. Thereafter, in a third basic operation state of each read/write bus cycle, the microcomputer reads data from the memory or write data to the memory.
In the case of searching or writing a large volume of data on a continuous address area, therefore, an address must be supplied to the address bus for each item of data. As a result, if the amount of data to be handled is increased, a total time used for a required number of read/write cycles is inevitably increased. In ordinary cases, for a time of period in which an address is being supplied to the bus, the microcomputer is put in a data waiting condition. Therefore, if a large amount of data is to be reference in the search processing, the wait time of the microcomputer will be increased in proportion to the amount of data to be referenced, with the result that the processing capacity of the microcomputer is greatly decreased.